Semiconductor memories are used in many electronic systems to store data that may be retrieved at a later time. As the demand for electronic systems to be faster, have greater computing ability, and consume less power has increased, semiconductor memories that may be, accessed faster, store more data, and use less power have been continually developed to meet the changing needs. Part of the development includes crewing new specifications for controlling and accessing semiconductor memories, with the changes in the specifications from one generation to the next directed to improving performance of the memories in the electronic systems.
Semiconductor memories are generally controlled by providing the memories with command signals, address signals, clock signals, the various signals may be provided by a memory controller. The command signals may control the semiconductor memories to perform various memory operations, for example, a read operation to retrieve data from a memory, and a suite operation to store data to the memory. With newly developed memories, the memories may be provided with system clock signals that are used for timing command signals and, address signals, for example, and further provided with data clock signals that are used for timing read data provided by the memory and for timing write data provided from the memory.
In typical designs read data is provided by a memory at a known timing relative to receipt of an associated read command by the memory. The known timing is defined by read latency information RL. Similarly, write data is received by a memory at a known timing relative to receipt of an associated write command by the memory. The known timing is defined by write latency information WL. The RL information and WL information are typically defined by numbers of clock cycles of the system clock signals. For example, RL information may define a RL, of 18 clock cycles of the system clock signals (tCKs). As a result, read data will be provided by a memory 18 tCKs after the read command is received by the memory. The RL information and WL information may be programmed in the memory by a memory controller.
With regards to memory designs using data clock signals, the data clock signals are provided to a memory (e.g., from a memory controller) to synchronize provision of read data or receipt of write data by the memory. The data clock signals are provided according to a specification to have a timing following the receipt of a memory command in order to provide data or receive data sufficient to meet the RL/WL information. The memory responds to the active data clock signals and provides or receives the data accordingly.
With the desire for faster performing memories, faster clock signals are used to clock the memories. The faster clock signals, however, present greater challenges for memories to perform any associated memory operations and with the correct timing.